1. Field
Exemplary embodiments of the present invention relate to a nonvolatile memory device, and more particularly, to a page buffer circuit and a nonvolatile memory device having the same.
2. Description of the Related Art
Memory devices are provided as internal storage devices of systems, for example, computers. The memory devices include an array of memory cells for storing data (hereinafter, referred to as a memory cell array) and row and column decoder circuits coupled to the memory cell array and configured to access the memory cell array in response to an external address.
One type of memory includes a nonvolatile memory known as, for example, a flash memory. The flash memory includes a memory cell array configured to store data and a plurality of page buffers configured to read data.
The memory cell array includes a plurality of strings which are electrically coupled to the respective page buffers through bit lines. Furthermore, each of the strings includes a plurality of memory cells coupled in series, and each of the memory cells includes a source, a drain, a floating gate, and a control gate.
The page buffer includes a bit line selector. The bit line selector is configured to select a bit line coupled to a string of the memory cell array. For example, the bit line selector includes bit line selection transistors composed of metal-oxide semiconductor field-effect transistors (MOSFET) and the like.
FIG. 1 illustrates a conventional page buffer circuit.
Referring to FIG. 1, the page buffer circuit may include a sensing circuit 101 and a bit line selection circuit 102.
A plurality of bit lines BL1 to BL6 are coupled to the bit line selection circuit 102 and selectively coupled to the sensing circuit 101 by the bit line selection circuit 102. The bit line selection circuit 102 includes a plurality of selection transistors 111A, 111B, 112A, 112B, 113A, and 113B having gates coupled to a selection line BSLe or BSLo in common. The plurality of bit lines BL1 to BL6 are coupled to the sources/drains of the selection transistors 111A, 111B, 112A, 112B, 113A, and 113B, respectively.
In FIG. 1, the plurality of bit lines BL1 to BL6 are formed at the same level. Therefore, coupling interference may occur between adjacent bit lines.